The present invention relates to packaging electronic integrated circuit chips into operable chip systems in a manner to facilitate testability. More particularly, the present invention relates to a method and configuration employing one or more removable overlay layers containing interconnection metallization patterns. Even more particularly, in one embodiment of the present invention, test chips are packaged with the system chips to exercise the system in its final configuration.
The present invention is generally directed to a method for interconnecting integrated circuit chips so as to allow them to be tested in their final configuration in terms of speed, operating environment packaging, temperature, voltage and proximity to other chips of the system. In the present invention, a removable overlay layer is applied to chips positioned on a substrate. The interconnection pattern of the overlay layer is specifically designed to partition the system for easy testing. The interconnect density of the overlay structure and its very low capacitive loading permit the utilization of extremely high density patterns which can make interconnection to a chip possible, otherwise, chip systems cannot easily be tested. Probe stations are inadequate for such purposes because too many probes would be required or because the chip pads are too small to accommodate a probe or because the capacitive loading of the probe station is too high to allow the chip to operate at maximum speed.
Special test chips may also be employed herein These test chips are placed on the substrate along with the operating chip or chip system for the purpose of testing circuits at speeds and under operating conditions which cannot be duplicated at the wafer probe level.
The overlay layer employed herein is removable and there is no resulting degradation to the underlying chip. The overlay layer can be removed and reapplied several times if necessary with different wiring configurations and with removal and replacement of defective chips until the final operating configuration is established. Alternate overlay configurations are possible. In one configuration, inferior, but easily processed materials are used to provide a test overlay layer thereby simplifying the process and exposing the chips to less stringent processing conditions. In a second configuration, a test overlay layer is applied over an already in place overlay layer for the purpose of simplifying partitioning and multiprobe testing of a complex system.
The method and configuration of the present invention is unique in that chips can be arranged in their final operating positions, and connected for the purpose of testing. Then all connections are removed and are reconnected in an operating configuration. Other interconnect systems, including hybrid circuits, printed circuits and hard-wiring are not amenable to easy removal of all interconnects and reapplication of the interconnections in a different form.
The problem to be solved is a multi-faceted one. The generic problem is to test a system at the lowest feasible functional level to identify defective parts so that a completely functioning system with a high degree of assured reliability can be produced. A first set of problems results from the deficiency of probing chips at the wafer level. Wafer probers are limited in speed of the chips that they can test due to the relatively long runs and high capacitive loading associated with the probes. Wafer probes are also limited in the total number of chip pads which can be probed at one time. Wafer probes are also limited by the minimum size of the pad which can be probed. This limitation is exacerbated by large numbers of pads. Additionally, increased pin count is also becoming more prevalent with the advent of very large scale integration since more complexity can now be put on a given chip.
Another problem exists in testing systems where several chips must be interconnected to perform a given function. In particular, it may be impossible to detect a defective part until it is interconnected with other parts of the functional block. Examples of such cases include multiple chip microprocessor systems, fast fourier transform systems in which the system size is too large for a single chip, large parallel multiplying systems, and memory systems. It is possible to test the functional blocks after they are assembled into a complete system. However, testing would they be extremely complex and time consuming due to the constraints imposed by the large number of parameters which must be tested.
An additional problem is testing chips under burn-in conditions. The typical burn-in involves operating the system typically for a period of approximately 100 hours at high temperature conditions. Experience has shown that if a chip is apt to fail, it generally fails under these conditions within the 100 hour time period. The conventional approach to testing chips is to first test the chip at the probe station, recognizing deficiencies in the number of probes and in speed. The chips which pass these tests are packaged. In high reliability systems, the packaged chips are burned-in under power. After burn-in, the package chips are tested again to determine proper functionality. The packaged chips are then interconnected on a printed circuit board to form the final system. Because of size and speed constraints, it is desirable to incorporate several chips in the same package. This complicates burn-in because one failed chip in a package requires that the whole package, including all the good chips, be discarded. The high density interconnect system disclosed herein uses an overlay layer to provide a method for directly connecting a large number of chips within the same package. The invention disclosed herein provides a method for the complete test and burn-in of the chip as well as a practical method for partitioning the system into manageable blocks which are easily tested. In addition, in an alternate configuration in which the test layer is added after the overlay layers have been interconnected, a removable overlay layer can be used to provide a multiplicity of connections throughout the rest of the system for the purpose of system testing and debugging during and after burn-in. This approach provides the rough equivalence of a " bed of nails" test fixture which is typically used for printed circuit boards but on a pitch of 1 mil rather than a pitch of 50 mils.